1. Field of Invention
This invention relates to a semiconductor process, and particularly relates to a semiconductor process for integrated fabrication of memory cells and other devices.
2. Description of Related Art
In order to improve the speed of data storage and reading, memory cells and other devices may be integrated in the same chip.
When the memory cells are charge-trapping non-volatile memory cells and need a charge-trapping layer under the gates, the gate dielectric layer of other devices needs a separate step to form. Moreover, in cases where the other devices include two kinds of devices, such as high-voltage (HV) devices and low-voltage (LV) devices, their gate dielectric layers may be formed separately to create two gate dielectric thicknesses.
In a conventional method for forming such structure, an ONO layer as a charge-trapping layer required by the memory area is formed, the portions of the ONO layer in the HV device area and LV device area are removed, a thicker gate oxide layer required by the HV devices is formed in the exposed HV device area and LV device area, the portion of the thicker gate oxide layer in the LV device area is removed, and then a thinner gate oxide layer is formed in the exposed LV device area.
However, for the thicker gate oxide layer required by the HV devices has ever been formed in the LV device area that is smaller, the stress caused by growing the thicker gate oxide layer may induce defects in the substrate of the LV device area. The substrate defects will cause device leakage problems.